Design Rule Verification Report
Date:
11/19/2025
Time:
1:19:35 PM
Elapsed Time:
00:00:00
Filename:
C:\Users\Public\Documents\Altium\Breakout Box\Breakout_Box_MDM25.PcbDoc
Warnings:
0
Rule Violations:
14
Summary
Warnings
Count
Total
0
Rule Violations
Count
Clearance Constraint (Gap=10mil) (All),(All)
4
Short-Circuit Constraint (Allowed=No) (All),(All)
0
Un-Routed Net Constraint ( (All) )
4
Modified Polygon (Allow modified: No), (Allow shelved: No)
0
Width Constraint (Min=10mil) (Max=10mil) (Preferred=10mil) (All)
0
Routing Topology Rule(Topology=Shortest) (All)
0
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)
0
Hole Size Constraint (Min=1mil) (Max=100mil) (All)
4
Hole To Hole Clearance (Gap=10mil) (All),(All)
0
Minimum Solder Mask Sliver (Gap=10mil) (All),(All)
2
Silk To Solder Mask (Clearance=10mil) (IsPad),(All)
0
Silk to Silk (Clearance=10mil) (All),(All)
0
Net Antennae (Tolerance=0mil) (All)
0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)
0
Total
14
Clearance Constraint (Gap=10mil) (All),(All)
Clearance Constraint: (7.218mil < 10mil) Between Hole of Pad J1-(6295mil,2337.008mil) on Multi-Layer And Pad J1-1(6315mil,2420mil) on Multi-Layer
Clearance Constraint: (7.218mil < 10mil) Between Hole of Pad J1-(6295mil,3302.992mil) on Multi-Layer And Pad J1-13(6315mil,3220mil) on Multi-Layer
Clearance Constraint: (9.39mil < 10mil) Between Hole of Pad J2-26(1840mil,2332.5mil) on Multi-Layer And Pad J2-1(1820mil,2415mil) on Multi-Layer
Clearance Constraint: (9.39mil < 10mil) Between Hole of Pad J2-27(1840mil,3297.5mil) on Multi-Layer And Pad J2-13(1820mil,3215mil) on Multi-Layer
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Un-Routed Net Constraint ( (All) )
Un-Routed Net Constraint: Via (1770mil,1925mil) from Top Layer to Bottom Layer Dead Copper - Net Not Assigned.
Un-Routed Net Constraint: Via (1770mil,3650mil) from Top Layer to Bottom Layer Dead Copper - Net Not Assigned.
Un-Routed Net Constraint: Via (6335mil,1930mil) from Top Layer to Bottom Layer Dead Copper - Net Not Assigned.
Un-Routed Net Constraint: Via (6335mil,3645mil) from Top Layer to Bottom Layer Dead Copper - Net Not Assigned.
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Hole Size Constraint (Min=1mil) (Max=100mil) (All)
Hole Size Constraint: (129.921mil > 100mil) Via (1770mil,1925mil) from Top Layer to Bottom Layer Actual Hole Size = 129.921mil
Hole Size Constraint: (129.921mil > 100mil) Via (1770mil,3650mil) from Top Layer to Bottom Layer Actual Hole Size = 129.921mil
Hole Size Constraint: (129.921mil > 100mil) Via (6335mil,1930mil) from Top Layer to Bottom Layer Actual Hole Size = 129.921mil
Hole Size Constraint: (129.921mil > 100mil) Via (6335mil,3645mil) from Top Layer to Bottom Layer Actual Hole Size = 129.921mil
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Minimum Solder Mask Sliver (Gap=10mil) (All),(All)
Minimum Solder Mask Sliver Constraint: (9.39mil < 10mil) Between Pad J2-1(1820mil,2415mil) on Multi-Layer And Pad J2-26(1840mil,2332.5mil) on Multi-Layer [Top Solder] Mask Sliver [9.39mil] / [Bottom Solder] Mask Sliver [9.39mil]
Minimum Solder Mask Sliver Constraint: (9.39mil < 10mil) Between Pad J2-13(1820mil,3215mil) on Multi-Layer And Pad J2-27(1840mil,3297.5mil) on Multi-Layer [Top Solder] Mask Sliver [9.39mil] / [Bottom Solder] Mask Sliver [9.39mil]
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